A signal processing system of EW digital receiver is introduced.It is based on FFT/IFFT algorithm,and realized completely by FPGA and constructed annularly.The four FPGAs in the system implement respectively high-speed data transmission interface, FFT/IFFT operation and signal detection in time/frequency domain. The system can do 1~1024K points FFT operation, 1~64K points IFFT operation and can detect the parameters of pulse description word for 4simultaneous-arrival signals at most. The FPGAs in the system run with distributed, multi-bus, parallel and pipeline mode and they need only about 20ms to detect 4signals while 256K-point FFT and 32K-point IFFT are adopted.