Design and implementation of BeiDou signal fast acquisition algorithm based on FPGA+DSP
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Open Fund Project of Graduate Innovation Base (Laboratory) of Nanjing University of Aeronautics and Astronautics

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    Abstract:

    In BeiDou satellite receiver, a fast BeiDou signal acquisition algorithm based on coherent down-sampling is proposed to solve the problem that the large amount of data to be processed by the Fourier transform affects the acquisition speed of satellite signals in the traditional parallel frequency acquisition algorithm. The coherent down-sampling module is added to the traditional parallel frequency acquisition algorithm. After the carrier and pseudo random code are stripped, the sampling frequency is reduced to reduce the number of points to be processed in the Fourier transform, and then a three-dimensional search on the satellite signal is performed. This algorithm is designed and implemented with FPGA+DSP (field-programmable gate arrays + digital signal processors). Theoretical analysis shows that the algorithm can reduce the amount of calculation by more than 80%. The experiments of the actual BeiDou signal show that the average acquisition time of each star is 9.95ms, and the memory resource consumption is reduced by 42% compared with the traditional parallel frequency acquisition algorithm. This algorithm can effectively improves the acquisition speed while saving resources, thereby realizing the rapid acquisition of BeiDou satellites.

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History
  • Received:September 03,2020
  • Revised:October 13,2020
  • Adopted:October 13,2020
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