基于FPGA的通用卷积层IP核设计
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国防科技重点实验室课题(6142205190401)


Design of universal convolutional layer IP core based on FPGA
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    摘要:

    针对目前卷积神经网络在小型化、并行化过程中遇到的计算速度不够、可移植性差的问题,根据卷积神经网络和FPGA器件的特点,提出了一种利用VHDL语言参数化高速通用卷积层IP核的设计方法。利用卷积层的计算方式,将卷积核心设计为全并行化、流水线的计算模块,通过在卷积核心的每一行连接FIFO的方式改善数据流入的方式,减少地址跳转的操作,并加入控制核心使其可以随图像和卷积窗口大小调整卷积层参数,生成不同的卷积层,最后将卷积层与AXIS协议结合并封装成IP核。结果表明,在50 MHz的工作频率下,使用2×2大小的卷积核对100×100的图像进行卷积计算,各项资源利用率不超过1%,耗时204 μs,计算速度理论上可以达到最高5 MF/s。因此,设计方案在增加卷积模块可移植性的同时又保证了计算速度,为卷积神经网络在小型化器件上的实现提供了一种可行的方法。

    Abstract:

    Aiming at the problems of insufficient computing speed and poor portability in the miniaturization and parallelization of convolutional neural network,this paper proposes a design of high-speed universal convolutional layer IP core using VHDL language based on the characteristics of convolutional neural network and FPGA devices.Layer based on convolution calculation,convolution core design is put forward for the parallel calculation and pipeline module,through each line in the convolution of the core connect to FIFO to improve the data flow,reduce the operating address jump,and join the control core to make it can adjust the convolution with images and convolution window size to layer parameters,generate different convolution layer,finally,the convolution layer is combined with the AXIS protocol and encapsulated into IP core.Under the working frequency of 50 MHz,the convolution calculation of 100×100 images with 2×2 convolution check is carried out.The utilization rate of each resource is less than 1%,and the time is 204 μs.The theoretical calculation speed can reach the maximum of 5 MF/s.[JP]The IP core structure of the convolutional layer not only increases the portability of the convolutional module,but also ensures the computing speed,which provides a feasible implementation method for the implementation of convolutional neural network on miniaturized devices.

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安国臣,袁宏拓,韩秀璐,王晓君,侯雨佳.基于FPGA的通用卷积层IP核设计[J].河北科技大学学报,2021,42(3):241-247

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  • 收稿日期:2020-12-29
  • 最后修改日期:2021-05-07
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  • 在线发布日期: 2021-07-08
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